uvm_axi
AXI BFM
An open-source AXI BFM that provides a bus functional model for checking the standard protocol and analyzing transfer operations.
uvm AXI BFM(bus functional model)
234 stars
20 watching
113 forks
Language: Verilog
last commit: over 11 years ago
Linked from 1 awesome list
ben-marshall/awesome-open-hardware-verificationRelated projects:
| Repository | Description | Stars |
|---|---|---|
 aifeg/benchlmm | An open-source benchmarking framework for evaluating cross-style visual capability of large multimodal models | 84 |
 alexforencich/verilog-axis | Provides a collection of Verilog modules and wrappers for designing AXI stream bus components in FPGAs. | 750 |
 wyvernsemi/pcievhost | Generates PCIe traffic and supports logic simulation environments | 86 |
 raysalemi/uvmprimer | Compiled and simulated UVM Primer book examples for easy testing and learning | 495 |
 muziqiushan/vim-bufonly | A Vim plugin that restricts the current buffer to a single window and removes unnecessary buffers. | 0 |
 practical-uvm-step-by-step/practical-uvm-step-by-step | An open source project providing step-by-step examples and resources for learning and implementing the Unified Verification Methodology (UVM) in Verilog | 177 |
 bfmartin/fvwm-config-on-openbsd | A configuration project for a lightweight desktop environment using the FVWM window manager on OpenBSD. | 53 |
 zipcpu/wb2axip | An open-source Verilog project providing optimized bus bridges and components for high-performance interconnects. | 496 |
 taichi-ishitani/tvip-axi | An AMBA AXI4 VIP implementation in SystemVerilog | 363 |
 uvvm/uvvm | A methodology and tool suite for creating structured VHDL-based testbenches for FPGA and ASIC development | 377 |
 osvvm/osvvm | A comprehensive VHDL verification utility library with advanced testing and verification capabilities | 228 |
 manifest-cyber/aibom | A community-driven wiki and repository for documenting AI/ML bills of materials (BOMs) and promoting transparency into AI models. | 33 |
 pulp-platform/axi | Provides reusable IP modules and verification infrastructure for designing high-performance on-chip communication networks adhering to AXI standards. | 1,134 |
 boldingbruggeman/getm-rewrite | A Python and Fortran-based implementation of the General Estuarine Transport Model | 6 |
 bbci/bbci_public | A toolbox for online experiments and offline analysis of Brain-Computer Interface (BCI) signals in MATLAB. | 155 |