vunit

HDL tester

Automates testing of HDL code through unit tests and testbenches

VUnit is a unit testing framework for VHDL/SystemVerilog

GitHub

750 stars
51 watching
266 forks
Language: VHDL
last commit: almost 2 years ago
Linked from 2 awesome lists

asicfpgasystemverilog-hdltestbenchunit-testinguniversal-verification-methodologyverificationverilog-hdlvhdl

Screenshot of VUnit/vunit website

vunit.github.io/

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