OpenRAM
SRAM designer
A software framework that automates the design and layout of static random access memory (SRAM) circuits.
An open-source static random access memory (SRAM) compiler.
845 stars
57 watching
204 forks
Language: Python
last commit: 12 months ago
Linked from 1 awesome list
gdsmagicnetgennetlistsngspicepythonsram
Related projects:
| Repository | Description | Stars |
|---|---|---|
| | A tool for generating black-boxed SRAMs for use in CAD flows. | 34 |
| | Design and layout of an 8x8 SRAM memory array with a 3-to-8 decoder for accessing the SRAM array | 66 |
| | Defines data schema for chip design using Protocol Buffer schema definition language | 28 |
| | A framework for designing and verifying digital hardware using the Dart programming language | 377 |
| | A compiler for designing and generating layouts of memory compilers using DFF/Latch cells | 137 |
| | A toolset for designing and programming customized co-processors with a focus on flexibility and customizability | 147 |
| | A collection of MyHDL cores and tools for complex digital circuit design | 85 |
| | A tool for designing and simulating custom electronic circuits with support for hierarchical and parametric design approaches | 341 |
| | An RTL-to-GDSII flow tool for rapid semiconductor digital design | 1,660 |
| | Tools to program and manage STM32 microcontrollers using Rust | 3 |
| | A collection of design benchmarks and instances for evaluating and presenting digital circuit designs | 24 |
| | A Python-based language and toolchain for designing and synthesizing digital hardware | 1,592 |
| | A tool that analyzes and verifies the timing of digital designs using standard file formats. | 418 |
| | Library that provides a unified API to interact with various Large Language Models (LLMs) | 367 |
| | A Haskell-based compiler for hardware description languages like VHDL, Verilog, and SystemVerilog. | 1,451 |