riscv-ida
RISC-V disassembler
A Python-based RISC-V processor module for disassembling and emulating IDAPro binaries
RISC-V ISA processor module for IDAPro 7.x
29 stars
2 watching
4 forks
Language: Python
last commit: about 6 years agoRelated projects:
| Repository | Description | Stars |
|---|---|---|
 idapython/src | Tools and scripts for interacting with the IDA Pro disassembler | 1,435 |
 l4ys/lazyida | Improves the IDA Pro disassembly experience by introducing automated formatting and shortcut functionality. | 1,104 |
 crytic/ida-evm | A Python-based toolset for reverse-engineering Ethereum Virtual Machine (EVM) binaries | 311 |
 avast/retdec-idaplugin | Decompiles binary code from various architectures into human-readable assembly code | 765 |
 ioncodes/ida_scripts | A collection of Python scripts and tools for manipulating and analyzing data from IDA Pro disassembler output. | 2 |
 chipsalliance/riscv-dv | An instruction generator for RISC-V processor verification | 1,036 |
 pfalcon/scratchabit | A Python-based disassembler tool with data/control flow analysis capabilities for reverse engineering | 397 |
 swackhamer/ida_scripts | Python scripts for interacting with IDA disassembler | 12 |
 sifive/prockami | Formal verification and implementation of RISC-V processor designs using Coq. | 22 |
 arizvisa/ida-minsc | Provides a scripting interface to IDAPython's features for reverse engineering | 320 |
 wisk/medusa | An interactive disassembler for reverse-engineering and analyzing binary code | 1,045 |
 riscv-mcu/riscv-openocd | A fork of OpenOCD with RISC-V microcontroller support | 35 |
 openhwgroup/cve2 | A 32-bit RISC-V CPU core with a two-stage pipeline designed for low-cost embedded control applications. | 29 |
 cisco-talos/ghida | A plugin that integrates Ghidra decompiler into IDA Pro to provide a GUI-based reverse engineering tool | 781 |
 lanhikari22/gba-ida-pseudo-terminal | Tools for disassembling and analyzing Game Boy Advance game data using IDA Python commands | 13 |