cvc

Circuit Validator

Checks CDL netlists for errors and circuit validity

CVC: Circuit Validity Checker. Check for errors in CDL netlist.

GitHub

22 stars
4 watching
1 forks
Language: C++
last commit: almost 2 years ago
Linked from 1 awesome list


Backlinks from these awesome lists:

Related projects:

Repository Description Stars
f18m/netlist-viewer A tool for converting and visualizing electrical circuit designs from text format to graphical schematic. 40
diffblue/cbmc A tool for verifying the correctness and safety of C++ programs 863
mxmxmx/o_c Generates CV signals based on user input and stores them in a polymorphic format 474
fvutils/pyvsc Provides tools and techniques for generating testable digital circuits and analyzing their coverage 115
byuccl/spydrnet A framework for analyzing and transforming FPGA netlists 92
ailab-cvc/seed-bench A benchmark for evaluating large language models' ability to process multimodal input 322
evgeniums/cpp-validator A C++ header-only library for declaratively defining data validation constraints and applying them to various data structures 58
pulp-platform/common_cells A collection of reusable Verilog systemVerilog modules used to synchronize clocks and handles asynchronous crossings in digital circuits 531
eudoxia0/cmacro Provides a set of reusable code transformations and abstractions for writing domain-specific languages (DSLs) in C. 887
cfelton/rhea A collection of MyHDL cores and tools for complex digital circuit design 85
mciepluc/cocotb-coverage Tools for enhanced verification of digital circuits 106
asyncvlsi/act Asynchronous circuit design and simulation tools using a hardware description language. 102
theleoborges/bouncer A validation DSL for Clojure & Clojurescript applications 364
jbyuki/carrot.nvim A plugin for evaluating Lua code blocks in Markdown documents within Neovim 24
veridise/picus Automated tool for verifying uniqueness properties in zero-knowledge proof circuits 70