spydrnet
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
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Language: Python
last commit: 7 months ago cadcircuitcircuit-analysiscircuit-designcircuitscomputer-aided-designdigitaledaedifelectronic-design-automationfpgafpgashardwarehardware-designsnetlistnetlist-parsernetliststransformationtransformations