SMT-based-STDCELL-Layout-Generator
Cell layout generator
Automates layout generation for standard cells in digital circuits using SMT-based methods
SMT-based-STDCELL-Layout-Generator
16 stars
1 watching
6 forks
Language: Perl
last commit: over 3 years ago Related projects:
Repository | Description | Stars |
---|---|---|
| Automated tool for generating layout designs for standard cells in VFET technology using SMT-based methods | 3 |
| A tool that generates layout designs for digital integrated circuits using simulated annealing optimization | 16 |
| A tool for generating standard cell layouts using SMT based techniques | 17 |
| A Python-based tool for creating and manipulating 2D GDS layouts and CAD geometries. | 202 |
| Converts Inkscape SVG drawings to KiCad PCB designs with customizable footprints and layers. | 806 |
| Enables programmatic CSS generation within Pharo Smalltalk | 18 |
| A plugin for SBT that facilitates the creation of static web pages for projects | 321 |
| Automates analog IC layout generation | 215 |
| Provides a format and tools for creating graphical representations of electronic circuits using SVG images | 14 |
| A utility for generating responsive React components with built-in layout flexibility | 7 |
| A JUCE component for designing 2D isomorphic layouts based on MOS scales. | 2 |
| Automatically generates analog circuit layouts from unannotated netlists | 272 |
| A QuickCheck-inspired testing library for OCaml that enables property-based testing and random value generation. | 354 |
| A collection of reusable Verilog systemVerilog modules used to synchronize clocks and handles asynchronous crossings in digital circuits | 531 |
| Generates KiCad design rules from a human-readable table of voltage distances | 8 |