SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
Layout generator
A tool that generates layout designs for digital integrated circuits using simulated annealing optimization
SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
16 stars
2 watching
7 forks
Language: Perl
last commit: over 4 years ago Related projects:
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