SMT-based-STDCELL-Layout-Generator-for-VFET
Layout generator
Automated tool for generating layout designs for standard cells in VFET technology using SMT-based methods
3 stars
2 watching
2 forks
Language: SMT
last commit: almost 3 years ago Related projects:
Repository | Description | Stars |
---|---|---|
| Automates layout generation for standard cells in digital circuits using SMT-based methods | 16 |
| A tool that generates layout designs for digital integrated circuits using simulated annealing optimization | 16 |
| A tool for generating standard cell layouts using SMT based techniques | 17 |
| A plugin for SBT that facilitates the creation of static web pages for projects | 321 |
| Converts Inkscape SVG drawings to KiCad PCB designs with customizable footprints and layers. | 806 |
| A JUCE component for designing 2D isomorphic layouts based on MOS scales. | 2 |
| A Python-based tool for creating and manipulating 2D GDS layouts and CAD geometries. | 202 |
| A library of reusable SVG pictograms as Svelte components for building user interfaces | 120 |
| Provides a format and tools for creating graphical representations of electronic circuits using SVG images | 14 |
| Enables programmatic CSS generation within Pharo Smalltalk | 18 |
| Automates analog IC layout generation | 215 |
| A utility for generating responsive React components with built-in layout flexibility | 7 |
| Provides a basic template for building ARM projects with GCC using the STM32F0 microcontroller | 125 |
| A repository of pre-validated designs and models for the AMS Keil Graphics Driver (KGD) | 36 |
| Generates KiCad design rules from a human-readable table of voltage distances | 8 |