abc
Digital circuit design tool
A system for designing and verifying sequential digital circuits
ABC: System for Sequential Logic Synthesis and Formal Verification
919 stars
39 watching
594 forks
Language: C
last commit: 11 months ago
Linked from 1 awesome list
Related projects:
| Repository | Description | Stars |
|---|---|---|
| | Formalizations of compiler design and virtual machine calculations in Coq | 30 |
| | Generates Makefiles to synthesize and route digital circuits from Verilog designs using Vivado | 93 |
| | A Haskell implementation of software transactional memory for concurrent programming | 99 |
| | A resurrected and improved implementation of the LLVM C Backend in Groff, enabling compilation of programs written in various programming languages to native machine code. | 127 |
| | Automated verification of higher-order programs using separation logic | 57 |
| | A compiler for a toy language based on LLVM that implements the System Fω type-system | 103 |
| | A polyphonic synthesizer with 4 oscillators and stereo FX, supporting JACK, ALSA, LV2, and OSC. | 40 |
| | Asynchronous circuit design and simulation tools using a hardware description language. | 102 |
| | A Haskell-based compiler for hardware description languages like VHDL, Verilog, and SystemVerilog. | 1,451 |
| | An experimental implementation of a Haskell-like language with Racket's macro system | 1,167 |
| | An analog modelling software synthesizer with features like oscillators, envelopes and effects | 441 |
| | A collection of basic cryptographic algorithms implemented from scratch in C. | 1,847 |
| | A formalisation of Partial Commutative Monoids (PCMs) for verification of concurrent programs. | 26 |