OpenROAD
Design pipeline
An RTL-to-GDSII flow implementation for rapid digital design exploration and physical design implementation.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
2k stars
52 watching
556 forks
Language: Verilog
last commit: 7 days ago
Linked from 1 awesome list
cppdefedagdsiilefopendb-databaseopenroadrtltcltiming-analysisverilog
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