AutoSVA

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

GitHub
72 stars
6 watching
22 forks
Language: Python
last commit: 6 months ago
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designmethodology-developmentrtlsvasystemverilogverificationverilog

Screenshot of PrincetonUniversity/AutoSVA website

blog.yosyshq.com/p/community-spotlight-autosva/

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