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Pythonpushed over 2 years ago

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

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Testbench generator

Automatically generates formal testbenches to verify RTL module interactions based on signal annotations.

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View on GitHubblog.yosyshq.com/p/community-spotlight-autosva

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