AutoSVA
Testbench generator
Automatically generates formal testbenches to verify RTL module interactions based on signal annotations.
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
73 stars
6 watching
24 forks
Language: Python
last commit: 8 months ago
Linked from 1 awesome list
designmethodology-developmentrtlsvasystemverilogverificationverilog
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