Reduceron
FPGA processor
A Haskell-based implementation of a high-performance FPGA processor for running lazy functional programs with hardware garbage collection.
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
422 stars
26 watching
29 forks
Language: Haskell
last commit: 6 days ago compilerfpgahaskelllavaverilog
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