aes
AES encoder
An AES encryption core implementation in Verilog, supporting various key sizes and modes.
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
339 stars
27 watching
126 forks
Language: Verilog
last commit: almost 2 years agoLinked from 1 awesome list
aesasicblock-cipherencryptionfpga
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