OpenTimer
Timing analyzer
A tool for analyzing timing constraints in digital circuits
A High-performance Timing Analysis Tool for VLSI Systems
576 stars
48 watching
144 forks
Language: Verilog
last commit: almost 3 years ago
Linked from 1 awesome list
cadcircuit-analysiscircuit-simulationcircuit-simulatorcomputer-aided-designcpp17edaelectronic-design-automationparallel-computingstastatic-timing-analysisverilogvlsivlsi-circuitsvlsi-physical-design
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