digsim
digital simulator
A tool for simulating and analyzing digital logic circuits in an interactive environment.
An interactive digital logic simulator with verilog support (Yosys)
17 stars
3 watching
0 forks
Language: Python
last commit: 2 months ago
Linked from 1 awesome list
logicpythonrtlsimulationsimulatorvcdverilogyosys
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