SPDZ-Yao
Garbled circuit simulator
A toolset for benchmarking and simulating Yao's garbled circuit computation of SPDZ-2 code with optimized AES-NI support
Yao's garbled circuit computation of SPDZ-2 code
10 stars
2 watching
5 forks
Language: C++
last commit: about 7 years ago Related projects:
| Repository | Description | Stars |
|---|---|---|
 esonghori/tinygarble | A tool for implementing secure multi-party computations using Yao's Garbled Circuits | 119 |
 drahnr/oregano | An application for designing and simulating electronic circuits | 215 |
 flaport/sax | A tool for simulating and optimizing circuit behavior in the frequency domain using machine learning and parallel computing. | 75 |
 soegaard/6502 | An emulator and toolset for the 6502 CPU | 9 |
 mirage/ke | Fast implementation of queue data structure | 51 |
 efforg/crocodilehunter | Detects and tracks 4G cell site simulators in real-time | 970 |
 dmotz/turingtype | An animation library implementing a simple human typing simulation effect | 147 |
 ucb-bar/midas | Automated framework for converting digital circuit designs into FPGA-accelerated simulators | 98 |
 sezna/bigbang | Re-implementation of a C++ particle simulation in Rust for speed comparison purposes. | 38 |
 kev-cam/v2k-top | A software framework for parsing and simulating digital circuits described in Verilog and C++ languages. | 7 |
 pavel7004/graphplot | An open-source Go program for modeling and visualizing electrical circuits | 0 |
 upb-lea/pygeckocircuits2 | A Python wrapper around a circuit simulation tool | 5 |
 asyncvlsi/act | Asynchronous circuit design and simulation tools using a hardware description language. | 102 |
 galacticstudios/kicadverilog | Converts KiCad schematic designs into Verilog code to simulate and design digital circuits | 57 |
 fanny-yang/earlystoppingrkhs | Code for analyzing early stopping in kernel boosting algorithms | 0 |