UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
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Language: VHDL
last commit: 9 days ago
Linked from 2 awesome lists
ben-marshall/awesome-open-hardware-verification
vhdl/awesome-vhdl