OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
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Language: Verilog
last commit: over 1 year ago cadcircuit-analysiscircuit-simulationcircuit-simulatorcomputer-aided-designcpp17edaelectronic-design-automationparallel-computingstastatic-timing-analysisverilogvlsivlsi-circuitsvlsi-physical-design